1. Field of the Invention
The present invention relates to a test pattern selection apparatus, method and program for selecting a test pattern based on fault detection information acquired by employing a fault simulation from among a plurality of functional verification patterns relevant to an LSI or a functional block inside the LSI. In particular, the present invention pertains to a technique that makes it possible to achieve a fault coverage (fault detection rate) that is substantially identical to a value that can be expected in all functional verification patterns with functional verification patterns in number substantially fewer than the all functional verification patterns.
2. Description of the Related Art
In general, for each of the chips of manufactured LSIs, a shipment test (quality test) is carried out to check (select only conformance) prior to shipment that such LSIs are not faulty by employing test patterns that conveniently use and edit a plurality of verification patterns used for functional verification during development. In such shipment test, it is required that faults in LSI chips can be detected as reliably as possible by used test patterns. Thus, a fault coverage obtained by fault detection information extracting processing whose main means is fault simulation, a value of which is recognized to have a strong correlation with a product quality from the viewpoints of experience, is employed as a criterion to determine whether or not a test pattern can detect faults reliably. The xe2x80x9cfault coveragexe2x80x9d used here is a value that indicates how well faults can be detected with test patterns, for example, such as single stuck-at faults assumed in an LSI of a gate level description, in which basic cells composed of combinational logic gates (including primitive elements) and more complicated cells such as flip-flops are connected to each other. Each of the stuck-at faults, assumed 2xc3x97 number of connection nodes in total in an LSI, is defined for each connection node (wiring) to be fixed to 0 or 1.
In the meantime, although this fault coverage can be directly obtained by fault simulation employing verification patterns, in general, enormous CPU resources are required for fault simulation employing verification patterns. Moreover, in recent years, with advancement of large-scaled and complicated LSIs, the size of verification patterns (number of steps) rapidly increases. Further, it is essential to restrict the size of test patterns that can be stored in an LSI tester in order to carry out a shipment test at a reasonable cost. Thus, it becomes difficult to use such verification pattern intact as test patterns. At the present, it is indispensable to substantially reduce the number of verification patterns used as test patterns.
From such background, conventionally, there has been employed an approach that an LSI developer or function verification engineer selects verification patterns with a possible high fault coverage in consideration of the contents of verification patterns from among all verification patterns; checks the fault coverage for each pattern relevant to faults randomly sampled at a low rate by using such all verification patterns, and selects verification patterns with its high fault detection rate. However, there has been a problem that this approach is poor in efficiency and poor in reliability. In contrast, recently, as an efficient and reliable method, there are commercially available a functional verification coverage evaluation apparatus for analyzing how well verification patterns composed of a number of individual verification patterns achieves functional verification coverages (code coverages) relevant to RTL (Register Transfer Level) description of an LSI or a functional verification pattern selection apparatus for selecting a minimum number of verification pattern sets that achieve the same functional verification coverages as all verification patterns by using the result obtained for each verification pattern. (There are a few items for evaluating quality of functional verification. Consequently a few functional verification coverages are defined.) The result of the selection is used for shipment test pattern selection.
Here, test pattern selection processing employing such functional verification coverage evaluation apparatus and functional verification pattern selection apparatus will be briefly described with reference to FIG. 1.
In conventional test pattern selection processing, when a target LSI or RTL net 50 of a functional block in the LSI and verification patterns (in general, a set of a number of verification patterns) 51 are inputted to a test pattern selection apparatus 40, an RTL code coverage evaluation tool 41 extracts and outputs the functional verification coverages for each verification pattern. Then, a verification pattern selection tool 42 makes selections sequentially from a verification pattern with its high coverage relevant to functional verification items targeted for selection. In addition, this selection tool selects a minimum number of test patterns that achieves functional verification coverages equal to those of all test (verification) patterns. Lastly, when selected verification patterns 52, a net 53 at a gate level that corresponds to an RTL net 50 of the targeted LSI, a library 54 of a basic cell employed in the net 53, and an undetected fault list 55 (in general, automatically prepared by a fault simulator) before fault detection information extraction presumed relevant to the net 53 are inputted to a fault simulator 43, thereby carrying out fault detection information extraction (fault simulation), a fault coverage indicating how well faults can be detected by (a set of) the verification patterns and an (undetected) fault list 56 is outputted. In this case, fault simulation employing individual verification patterns is executed for a (undetected) fault list of the results of fault simulation employing the previous verification patterns. Hereinafter, this simulation is referred to as xe2x80x9cincrementalxe2x80x9d fault simulation (fault detection information extracting processing) distinctly in particular.
According to such test pattern selection processing, in spite of a set of verification patterns that are significantly small as compared with all verification patterns, there can be obtained a fault coverage comparatively close to an expected fault coverage in the case where the full verification patterns are employed. This makes it possible to significantly reduce a CPU time required for extracting fault detection information relevant to an LSI below a gate level or a test pattern length at the time of shipment test.
However, such conventional test pattern selection processing has the following technical problems to be solved.
That is, the functional verification coverages obtained by the conventional test pattern selection processing activates functional verification items at the RTL description level of a targeted LSI in strict senses. The functional verification coverages are good indicators for the coverage of controllability in testability that is s scale indicating how reliably shipment test can be carried out in gate level description. However, the functional verification coverages are not always reliable as to observability. Even although the number of verification patterns can be significantly reduced, in the case where an attempt is made to ensure a fault coverage almost equal to that of all verification patterns, the fault coverage is effective as a first solution, but is somewhat lower (by some percents) than a fault coverage which would be obtained in all verification patterns.
In general, the analysis of undetected faults and preparation of additional verification patterns are difficult works requiring many engineer resources. Thus, the slight lowering of fault coverage is a very big problem. Therefore, it is expected to introduce a test pattern selection technique with its high efficiency capable of reliably achieving a fault coverage that is substantially identical to that of all test (verification) patterns with a small number of test patterns.
The present invention has been made in order to solve the foregoing technical problems. It is an object of the present invention to provide a computer readable recording medium storing a test pattern selection apparatus, method and program with its significantly high efficiency as compared with conventional apparatus, methods and programs.
According to a first aspect of the present invention, there is provided a test pattern selection apparatus comprising: a fault detection information extracting portion for employing selected test patterns from a set of test patterns discriminated to be selected or deselected in advance to execute incremental fault simulation, and employing an arbitrary deselected test pattern to execute fault simulation, and then, extract a fault coverage and a detected and undetected fault list; a random sampling processing portion for randomly sampling some of the faults in an undetected fault list; and a selecting portion for selecting test patterns that greatly contributes to improvement of a fault coverage in the deselected test patterns by referring to the detected and undetected fault list.
In this manner, a fault coverage almost equal to a value obtained with all verification patterns can be achieved with verification patterns (test patterns) significantly fewer than all verification patterns.
According to a second aspect of the present invention, there is provided a test pattern selection method comprising: a first test pattern selection step of selecting test patterns; a first fault detection information extracting step of employing the thus selected test patterns, thereby executing incremental fault simulation, and extracting a first undetected fault list; a random sampling processing step of randomly sampling some of undetected faults in the first undetected fault list to generate a second undetected fault list; a second fault detection information extracting step of employing the second undetected fault list and a deselected arbitrary test pattern in the first test pattern selection step, thereby executing fault simulation, and generating a detected and undetected fault list for each of the deselected test patterns; and a second test pattern selection step of selecting test patterns that greatly contributes to improvement of a fault coverage from among the deselected test patterns by referring to the detected and undetected fault list for each test pattern deselected.
In this manner, a fault coverage almost equal to a value obtained with all verification patterns can be achieved with verification patterns (test patterns) significantly fewer than all verification patterns.
According to a third aspect of the present invention, there is provided a test pattern selection program comprising: a first test pattern selection process of selecting test patterns; a first fault detection information extracting process of employing the thus selected test patterns, thereby executing incremental fault simulation, and extracting a first undetected fault list; a random sampling processing process of randomly sampling some of undetected faults in the first undetected fault list to generate a second undetected fault list; a second fault detection information extracting process of employing the second undetected fault list and a deselected arbitrary test pattern in the first test pattern selection step, thereby executing fault simulation, and generating a detected and undetected fault list for each of the deselected test patterns; and a second test pattern selection process of selecting test patterns that greatly contributes to improvement of a fault coverage from among the deselected test patterns by referring to the detected and undetected fault list for each test pattern deselected, the test pattern selection program causing a computer to execute these processes.
However, with respect to functional verification coverage evaluation process, first verification pattern selection processing, random sampling processing or fault detection information extracting processing, essentials of the processes in line with their respective purposes are stored as another program in another computer readable recording medium. A test pattern selection program may be responsible for execution and control of these processes (such as input and/or output of required data, each program startup).
In this manner, a fault coverage almost equal to a value obtained by all test patterns (verification patterns) can be achieved in test patterns significantly fewer than all test patterns.
In addition, an undetected fault list targeted for executing the incremental fault simulation may not always be all of the targeted LSIs, and may be part thereof. In particular, there may be described faults that cannot be detected and remain undetected using a testing approach other than that employing functional verification patterns and a fault simulation such as a scan test technique applied to a targeted LSI, thereby executing ATPG (Automatic Test Pattern Generation).
Further, functional verification coverage evaluation processing and first test pattern selection processing, as in a conventional manner, can be substituted by a method for manually selecting test patterns that may greatly contribute to improvement of a fault coverage by proper means. In this case, although it is not efficient, in the case where a fault coverage is too low in view of processing capability of a test pattern selection apparatus by referring to the results of the first fault detection information extracting, it may be required to further add test patterns, and improve the fault coverage, and then, perform the processing of random sampling and subsequent processes.
In addition, second test pattern selection processing desirably comprises: an additional detection fault number extracting process for computing the number of additional detection faults indicating how many undetected faults are detected in a reference undetected fault list by referring to the detected and undetected fault list for each test pattern deselected in a first test pattern selection process; an evaluation value computation process for computing an evaluation value for each test pattern deselected in the first test pattern selection process by a predetermined evaluation formula where the number of additional detection faults and a test pattern length are defined as inputs; and a selection process for selecting test patterns that greatly contribute to improvement of a fault coverage in the deselected test patterns in accordance with the computed evaluation value.
In addition, incremental fault simulation (fault detection information extracting processing) may be executed for final check by employing test patterns that greatly contribute to improvement of a fault coverage and a first undetected fault list.
With this additional process, with respect to undetected faults that has not been evaluated by random sampling processing as well, detected and undetected faults are clarified by the best patterns. Thus, the analysis of undetected faults of the targeted LSI and the generation of additional test patterns can be facilitated.
Further, in first fault detection information processing, a test pattern that does not meet a predetermined improvement value of fault coverage in test patterns selected by test pattern selection processing is added to test patterns (verification patterns) deselected by a test pattern selecting portion, whereby faults detected by the test pattern that does not meet the predetermined improvement value of fault coverage may be returned in an undetected fault list. Alternatively, with respect to such undetected fault list, in the case where the improvement of a predetermined fault coverage value is not found as a result of incremental fault simulation employing a certain test pattern, incremental fault simulation may be performed by employing an undetected fault list as a result of execution in a test pattern immediately preceding that test pattern together with the next test pattern (verification pattern).
With this construction, even if contribution to improvement of the functional verification coverages is found at a level of RTL, there occurs a possibility that test patterns with small contribution to improvement of a fault coverage is deselected at a gate level. Thus, a fault coverage almost equal to that of all test patterns can be obtained in smaller test pattern size.
Furthermore, in second test pattern selection processing, a plurality of test patterns may be selected at one processing operation.
With this construction, although there is a disadvantage that a slightly increased number of test patterns must be selected, the number of executions of additional detection fault number computation processing with a large amount of computations can be significantly reduced, thus enabling test pattern selection that more efficiently achieves a fault coverage almost equal to that of all test patterns.
Other and further objects and features of the present invention will become obvious upon understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.